Webinar Replay: 2nd Generation Intel® Hyperflex™ Architecture Overview for Intel Agilex™ Devices

Webinar Replay: 2^nd Generation Intel® Hyperflex™ Architecture Overview for Intel Agilex™ Devices

Delivering up to 40% higher core performance, or up to 40% lower power over Intel’s previous generation high-performance FPGAs, Intel^® Agilex™ FPGAs and SoCs are designed to help engineers to quickly deliver optimized Intel Xeon^® processor acceleration in the data center, tailored transformation in the network, and low-latency, real-time acceleration at the edge^†. In this webinar replay, you will:

Learn how the 2^nd generation Intel® Hyperflex™ architecture enables up to 40% higher core performance, or how the Intel® process helps reduce power by up to 40% lower power in Intel Agilex™ devices when compared to Intel’s previous generation high-performance FPGAs
Learn about the Hyper-Register, the basic building block of the HyperFlex architecture, and receive an overview of the three design techniques for taking advantage of Hyper-Registers, namely Hyper-Retiming, Hyper-Pipelining and Hyper-Optimization

Original Webinar date: Thursday, November 7, 2019

^†Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.

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Speaker

Marlon Price

Applications Engineer, FPGA Training Network and Custom Logic Group

Marlon Price has worked as an FPGA instructor for 18+ years, teaching thousands of engineers how to both create designs targeting FPGAs as well as how to get the most out of those FPGA designs. Using his expertise, he conducts live, in-person training courses as well as live over the internet classes. He has also produced hundreds of self-paced learning courses available on intel.com. His primary topics of focus are high-end FPGA design optimization, high-speed serial protocols and interfaces, 5G applications and algorithm acceleration using FPGAs.