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Webinar Replay: Introduction to Intel® Agilex™ FPGAs External Memory Interfaces Features

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Webinar Replay: Introduction to Intel® Agilex™ FPGAs External Memory Interfaces Features

Webinar Replay: Introduction to Intel® Agilex™ FPGAs External Memory Interfaces Features

Delivering up to 40% higher core performance, or up to 40% lower power over Intel’s previous generation high-performance FPGAs, Intel® Agilex™ FPGAs and SoCs are designed to help engineers quickly deliver optimized Intel Xeon® processor acceleration in the data center, tailored transformation in the network, and low-latency, real-time acceleration at the edge†. In this webinar replay, you will:

  • Learn how Intel Agilex FPGAs and SoCs provide up to 3.2 Gbps of DDR4 SDRAM interface
  • Learn the memory options that are available and how the architecture of Intel Agilex devices make such performance possible
  • Learn how to integrate an external memory interface into your design, including how to take advantage of resource sharing to implement multiple interfaces in a single device.

Original Webinar Date: January 16, 2020

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.

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Speaker

Steven Strell

Steven Strell

Applications Engineer, FPGA Training
Programmable Solutions Group

Steven Strell has worked as an FPGA instructor for 13 years, teaching thousands of engineers how to both create designs targeting FPGAs as well as how to get the most out of those FPGA designs. Using his expertise, he conducts live, in-person training courses as well as live over-the-internet classes. He has also produced hundreds of self-paced learning courses available on intel.com. His primary areas of focus are external memory interfaces, embedded system design, block-based design flows including partial reconfiguration, and hardware debugging tools and techniques.