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Webinar Replay: Introduction to Intel® Agilex™ PCIExpress* Features

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Webinar Replay: Introduction to Intel® Agilex™ PCIExpress* Features

Webinar Replay: Introduction to Intel® Agilex™ PCIExpress* Features

Delivering up to 40% higher core performance, or up to 40% lower power over Intel’s previous generation high-performance FPGAs, Intel® Agilex™ FPGAs and SoCs are designed to help engineers to quickly deliver optimized Intel Xeon® processor acceleration in the data center, tailored transformation in the network, and low-latency, real-time acceleration at the edge†. In this webinar replay, you will:

  • Learn how the Intel® Agilex™ F-Series FPGAs and SoCs provide up to 2X more PCIExpress* (PCIe*) bandwidth through PCIe* Gen41
  • Learn how the Intel® Agilex™ F-Series FPGAs and SoCs contain hard and soft intellectual property (IP) blocks to support up to Gen4 x16 at 16GT/s delivered through the P-Tile transceiver tile
  • Learn the architecture and key features of the P-Tile including endpoint, root port, and transaction layer protocol (TLP) bypass modes, port bifurcation, autonomous hard IP (HIP) mode, and Single Root I/O Virtualization (SR-IOV).

Original Webinar date: December 3, 2019

Original Webinar Time: 09:00 AM - 10:00 AM PT

1 Comparison based on PCIe* Gen.3 vs. PCIe* Gen.4 theoretical peak performance, based on PCI-SIG* specifications.

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.

* Other names and brands may be claimed as the property of others.

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Speaker

Marlon Price

Marlon Price

Applications Engineer, FPGA Training
Network and Custom Logic Group

Marlon Price has worked as an FPGA instructor for 18+ years, teaching thousands of engineers how to both create designs targeting FPGAs as well as how to get the most out of those FPGA designs. Using his expertise, he conducts live, in-person training courses as well as live over the internet classes. He has also produced hundreds of self-paced learning courses available on intel.com. His primary topics of focus are high-end FPGA design optimization, high-speed serial protocols and interfaces, 5G applications, and algorithm acceleration using FPGAs.