Agilex FPGAs built using Intel’s 10nm super fin technology, deliver an average of 50% higher performance and 40% lower power relative to prior generations. These innovations have resulted in 2X higher core fabric performance/watt leadership over competing 7nm FPGAs. This represents the largest ever gen-to-gen improvement in performance and power efficiency for Intel FPGAs. In addition, Agilex also delivers the second generation of disaggregated architecture, Intel’s first CXL coherency with Xeon, 116G transceivers, and the industry’s first and only FPGA core fabric to natively support both BFLOAT16 and TensorFloat32 numeric formats.

This session will highlight Intel’s next generation 224G FPGA transceiver technology, followed by a live demo of the world’s first 224G PAM4 transceiver test chip.

The world’s first and fastest 116G PAM4 transceiver makes its debut on Intel Agilex I-Series FPGAs. Designed and built on Intel’s advanced 10nm SuperFin technology, 116G PAM4 transceivers are capable of meeting the needs of existing and emerging connectivity standards. Together with 400G Ethernet and OTN protocols, I-Series FPGAs are ideal for wired, networking, data center, and cloud applications.

Intel Nios^® V soft processors are based on the open-source RISC-V Instruction Set Architecture. In this session, we will provide an overview of the first of the Nios V processor series, the Nios V/m. We will also talk about the hardware and software development flows using Nios V. Finally, you’ll learn about the growing Nios V ecosystem to help you get your design to market faster.

Performance needs are increasing. Thermal budgets are being driven lower. Algorithms were changing but are becoming optimized. For many markets, these three realities are driving the need for hardened custom logic solutions. These challenges must be addressed within a fixed time window to gain first mover advantages and optimize total cost of ownership. Only Intel offers developers a full range of silicon solutions to optimize platforms for performance, cost, power, flexibility, and time-to-market – from Intel Xeon processors to purpose-built ASICs.

Intel’s first generation IPU platform is here. Infrastructure acceleration optimizes workload performance by offloading the CPU with specialized FPGA based hardware accelerators. In this session, we’ll walk you through several workload acceleration examples:

• Open vSwitch
• NVMeoF (RoCEv2)
• OFED RDMA

Join us to learn how Intel IPUs lead the charge in Data Center infrastructure acceleration.

A critical component of the Data Center is the storage, traditionally responsible for low latency, efficient, and reliable data retention. As the disaggregated data center becomes reality, storage nodes are being asked to do more with the data in efforts to optimized processing and network resources. In this session, you’ll learn about modern smart storage architectures and the Intel technologies that make it all possible.

Building custom hardware platforms can be laborious. Even more so when a new Board Support Package (BSP) is needed for every single platform. That’s where Intel OFS simplifies BSP creation by abstracting the process to high-level flows like OpenCL and oneAPI. Follow Hitek Systems as they leverage OFS to develop their Agilex based PCIe accelerator card.

Upstreaming drivers to the Linux kernel is an ideal solution for developers to get native support from their software vendors, such as Red Hat. However, product timelines, resources, or bandwidth constraints might demand an intermediate solution. That's where the community driven backport driver created with the Red Hat^® Enterprise Linux^® operating system comes in. Join this session to learn more about how you can get your custom platform development enabled today for Intel^® Stratix^® 10 FPGAs, Intel^® Agilex^™ FPGAs, and future Intel^® FPGA device families.

In this session, you will learn about how Agilex^™, Intel’s latest family of high-end FPGAs, is enabling more compact, power and performance-optimized solutions to 4K and 8K video processing applications. You will also learn about Intel PSGs newest video and vision software solutions, including a new suite of 20+ in-house video and vision processing IP cores, new connectivity IP solutions for HDMI, DP, SDI, and HDCP, and how Intel is leveraging an in-house design services team to assist you in getting to market as soon as possible with your very own custom video application.

The new JPEG XS ISO standard specifies a compression technology for high quality video transport. Intel has a complete FPGA evaluation platform for this standard based on the Intel^® Cyclone^® 10 GX device: an easy way to implement JPEG XS for your embedded video and image processing application. In this session, we will explain JPEG XS advantages in quality, latency, and complexity and then demonstrate how FPGA developers can use our kit to easily evaluate JPEG XS and assess if it is the right technology for their video application requirements.

Intel has developed a complete FPGA-based cloud to edge solution with our partner Microsoft. This Azure certified device makes it easy to develop intelligent, highly scalable IoT products that can collect, analyze and react to data without much complexity. Analog Devices has enabled this platform to ingest and aggregate data from an almost limitless number of sensors.

The Small Grants Programme, a corporate programme of the Global Environment Facility (GEF) that is implemented by the United Nations Development Programme (UNDP), look towards the technology of Intel, Microsoft, and Analog Devices in Terasic’s design contest to bring innovative minds together to solve real-world sustainability challenges. Join us as team or follow along the most remarkable designs by visiting innovatefpga.com

Intel FPGAs power critical manufacturing applications through a diverse portfolio of production-ready solutions. Join us to explore the pre-built solutions that enable Intel and its partner ecosystem to turn Smart Factories into a reality.

This session will walk you through the value propositions that Intel FPGAs bring for your test and measurement applications. You will learn what relevant FPGA products can be leveraged to address various applications including ATE systems, RF instruments and scopes and the latest communication protocol testers.

As ASICs becoming increasingly complex, more advanced tools are needed to develop them. FPGAs have long been used as ASIC development platforms, largely due to flexibility and the ability to keep up with advancing standards in connectivity. In this session, you’ll learn how the Stratix^® 10 GX 10M FPGA combined with Quartus^® Prime Software are ideal for advanced ASIC prototyping and emulation.

As 5G deployments continue to rollout, the shift to Open RAN is necessary to meet demand. To improve time to market, Intel released FlexRAN reference software to efficiently implement wireless access workloads on Intel Xeon scalable processors. In this session, you’ll learn how Intel’s N6000 Acceleration Development Platform, an Intel Agilex FPGA-based SmartNIC, provides even greater scale for vRAN deployments - supporting more cell sites, and integrating a wide range of fronthaul, midhaul and backhaul connectivity for PCIe slot-limited servers.

Winston Neweb Corporation (WNC) produces E2E 5G vRAN/Open RAN solutions for telco service providers on IA and the leading 10nm technology product family. This session showcases WNCs latest generation commercial off the shelf (COTS) platform on 5G, including DU and CU servers (Intel ICX-SP and ICX-D based), next-generation programmable accelerators (Arrow Creek/N6000), and 5GNR O-RU. 5GNR O-RU was developed on FlexRAN architecture, delivering an ORAN compliant 5GNR network with the best performance and highest power efficiency while reducing the TCO for operators.

FPGAs are used extensively in network switches and routers for packet-processing but programming FPGAs requires experienced engineers writing RTL code. Designed for software programmers, P4 removes the RTL barrier to entry, improving engineering productivity while achieving high quality results.

MoSys’ Virtual Accelerator Engine family includes Stellar Packet Classification platform IP which leverages the P4 language and the Graph Memory Engine (GME) to search and classify packet headers as an alternative to TCAM functions. This session will provide IP performance details, target markets, and use cases

Session also covers a short overview of the MoSys Memory and Accelerator Engine IC’s, which can be attached to an FPGA to augment FPGA memory or add accelerators to handle such things as network telemetry, statistics and trTCM – Two Rate Three Color Marker metering capabilities